Dr. Sergio Iserte (HPC Researcher — IEEE Senior Member)
holds a B.S. in Computer Engineering (2011), an M.S. in Intelligent Systems (2014), and a Ph.D. in Computer Science (2018) from Universitat Jaume I (UJI), Spain. His early research focused on resource management and parallel runtime systems for large-scale computing facilities, laying the foundation for the influential work he would later carry out in dynamic and heterogeneous HPC systems.
He is currently a Senior Researcher in the Accelerators and Communications for HPC (AccelCom) group, led by Dr. Antonio J. Peña, within the Computer Sciences Department at the Barcelona Supercomputing Center (BSC). In parallel with his research duties, he teaches High-Performance Computing (HPC) at the Open University of Catalonia (UOC) and Artificial Intelligence (AI) at the International University of Catalonia (UIC).
Dr. Iserte’s research career has evolved along a clear and impactful trajectory, characterized by independence, innovation, and sustained scientific contributions. He has authored more than 20 journal papers in Q1 venues and top-tier HPC conferences, receiving distinctions such as best paper awards. His research spans parallel distributed programming models, dynamic resource and process management, in-network acceleration using SmartNICs, HPC workload modeling, and the application of AI methods to scientific simulations. His doctoral work on dynamic resource management led to the development of DMR, a recognized malleability framework adopted in various European projects and HPC centers.
He has been deeply involved in European, national, and industrial R&D initiatives, frequently assuming leadership roles such as work package coordinator or principal investigator. His contributions include key involvement in EuroHPC-JU projects such as EUPILOT and DEEP-SEA, the Spanish PERTE Chip initiative “Barcelona Supercomputing Center - Barcelona Zettascale Lab,” and industrial collaborations with NVIDIA focused on next-generation in-network computing technologies. His leadership also extends to organizing scientific workshops, chairing events, and contributing to community-building initiatives such as the MareNostrum Hackathon, which he independently leads, securing funding and attracting 30–50 participants annually. Furthermore, he serves as Co-Chair for the Dynamic Resources for HPC Consortium with the aim of bringing together international researchers to advance methodologies, standards, and software infrastructure for dynamic and adaptive supercomputing.
Dr. Iserte is an active and respected member of the international HPC community. He has served on more than 30 technical and organizational committees across major IEEE and ACM conferences—including IEEE Cluster, EuroMPI/USA, ICPP, and SC (in which he served in the technical, inclusivity, infrastructure, student, and security committees). He has reviewed over 200 scientific papers, book chapters, and research proposals for national funding agencies, and he has served as Executive Guest Editor for special issues in Journal of Parallel and Distributed Computing (JPDC) and Future Generation Computer Systems (FGCS).
He is also committed to mentorship and community building, supervising visiting researchers, engineers, undergraduate theses, master’s students, and Ph.D. candidates. Through his blend of research excellence, leadership, and service, Dr. Iserte contributes to shaping the future of high-performance computing.
His research interests primarily include:
- Parallel distributed programming models
- Dynamic resource management
- HPC-QC convergence
- HPC workload modeling
- In-network computing
- Applied artificial intelligence
See in this map all the places where science has taken him!
Memberships
